Lab Report: Kirchhoff’s Voltage And Current Laws (KVL And KCL)

Abstract: In this "Lab Report: Kirchhoff’s Voltage And Current Laws (KVL And KCL) Essay" we do our hand calculation to find the results based on the given values theoretically and write the values in the table. Then, we simulate the circuit in figure 3, of the lab handout 2, on Orcad software to get the values and compare it to our hand calculations. We draw the circuit at the lab handout then we do the actual circuit on the breadboard and by using the lab equipment the real measurements. After we put the values obtained by the lab devices in the tables we shall compare them to the simulated and calculated values.

Theory:

Kirchhoff’s Voltage and Current Laws (KVL and KCL) are basically conservation of electric energy or charge laws.

First, Kirchhoff’s Voltage Law states that the algebraic sum of all voltages around a closed loop is zero. Which means that if we add all the voltages of branches in closed path will equal to zero as this equation will explain more: V1+V2+V3+…+Vn=0 Kirchhoff’s Current Law states the sum of the currents entering a node equal to the sum of the currents leaving the node. Initially, a Node is the point or gate that’s connects to or more branches in order the flow of currents through them is possible. This equation will explain: Figure 2I1+I2+…+In=I3+I4+…+In Example on figure 2: I1+I3+I4=I2+I5

Procedures:

  1. At the beginning of the experiment we use the PC to open Pspice software and create a circuit which in the lab handout figure 4.
  2. Second, we simulate the circuit and put the obtained values in the table.
  3. Then, we should take the needed equipment like the breadboard, wires, and resistors where the types of resistors are (R1=1K, R2=2. 7K, R3=1. 8K, R4=4. 7K).
  4. Afterwards we open the Digital multimeter and the DC power supply.
  5. After opening the DC power supply, we modify the values of the voltage and current as follows respectively (12V and 0. 1A).
  6. Then, the resistors going to be measured by the DMM and put there values on the table without connecting them to the DC power supply.
  7. At this part we place the resistors on the breadboard and connect it to the DC power supply, however we must check for the values of the current and voltage were entered in the DC power supply, after making sure we open the output switch.
  8. Using DMM we measure the voltage across each resistor and put the values on the table.
  9. We also measure the current using DMM, however, we must break the circuit at the first terminal of the resistor that we need to measure. The values obtained must be written down in the table as well.
  10. At last we close all the devices were used at the experiment and take out the resistors from the breadboard and put them at the appropriate place.

Further Analysis: 1) Verify KVL in any loop of figure 4 circuit from the simulated pspice value. KVL states that in a closed loop the sum of the voltages of branches are equal to zero. These equations will verify this statement: -Vs+Vr1+Vr2=0-5v+1. 438v+3. 562v=0v2) Verify KCL in figure 3 circuit from hardware measurement. KCL states that the current entering a node is equal to the current leaving it. At the node between Ir1 and Ir2, Ir3 we can see that: Ir1=Ir2+Ir34. 127≈2. 91+1. 211

Conclusion: After all the work that was put into the lab it helped us and taught us how to use KVL and KCL in our calculations, how and when to use them and which circuits need us to use KCL and which of them need us to use KVL. First of all, we realized that with the use of KVL, we have to involve the loops in our calculations, observing how the circuit starts and ends and if the voltage of the elements is positive or negative depending on their terminals. We also noted that KCL calculations need us to look at the nodes and find out the relationship between the different currents flowing within the circuit. There also was another important observation in that, when we dealt with a circuit in which all of its elements are in parallel, KVL cannot be used since the voltages throughout each element is the same, therefore cancelling each other out, so the only solution in this case is to use KCL.

18 May 2020
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